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cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 18-mbit ddr ii sio sram two-word burst architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-58907 rev. *b revised february 25, 2011 features 18 mbit density (2 m x 8, 2 m x 9, 1 m x 18, 512 k x 36) 333-mhz clock for high bandwidth two-word burst for reducing address bus frequency double data rate (ddr) interfaces (data transferred at 666 mhz) at 333 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two input clocks for output data (c and c ) to minimize clock skew and flight time mismatches echo clocks (cq and cq ) simplify data capture in high-speed systems synchronous internally self timed writes ddr ii operates with 1.5 cycle read latency when doff is asserted high operates similar to ddr i devi ce with one cycle read latency when doff is asserted low 1.8 v core power supply with hstl inputs and outputs variable drive hstl output buffers expanded hstl output voltage (1.4 v?v dd ) ? supports both 1.5 v and 1.8 v i/o supply available in 165-ball fbga package (13 x 15 x 1.4 mm) offered in both pb-free and non pb-free packages jtag 1149.1 compatible test access port phase locked loop (pll) for accurate data placement configurations cy7c1392kv18 ? 2 m x 8 cy7c1992kv18 ? 2 m x 9 CY7C1393KV18 ? 1 m x 18 cy7c1394kv18 ? 512 k x 36 functional description the cy7c1392kv18, cy7c1992kv18, CY7C1393KV18, and cy7c1394kv18 are 1.8 v synchronous pipelined srams, equipped with ddr ii sio (double data rate separate i/o) architecture. the ddr ii sio consists of two separate ports: the read port and the write port to access the memory array. the read port has data outputs to support read operations and the write port has data inputs to support write operations. the ddr ii sio has separate data inputs and data outputs to completely eliminate the need to ?turnaround? the data bus required with common i/o devices. access to each port is accomplished through a common address bus. addresses for read and write are latched on alternate rising edges of the input (k) clock. write data is registered on the rising edges of both k and k . read data is driven on the rising edges of c and c if provided, or on the rising edge of k and k if c/c are not provided. each address location is associated with two 8-bit words in the case of cy7c1392kv18, two 9-bit words in the case of cy7c1992kv18, two 18-bit words in the case of CY7C1393KV18, and two 36-bit words in the case of cy7c1394kv18 that burst sequentia lly into or out of the device. asynchronous inputs include an output impedance matching input (zq). synchronous data outputs are tightly matched to the two output echo clocks cq/cq , eliminating the need to capture data separately from each i ndividual ddr ii sio sram in the system design. output data clocks (c/c ) enable maximum system clocking and data sy nchronization flexibility. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c (or k or k in a single clock domain) input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. table 1. selection guide description 333 mhz 300 mhz 250 mhz 200 mhz 167 mhz unit maximum operating frequency 333 300 250 200 167 mhz maximum operating current x8 440 420 370 330 300 ma x9 440 420 370 330 300 x18 450 430 380 340 310 x36 560 520 460 400 360 [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 2 of 31 logic block diagram (cy7c1392kv18) logic block diagram (cy7c1992kv18) 1 m x 8 array clk a (19:0) gen. k k control logic address register d [7:0] read add. decode read data reg. ld q [7:0] reg. reg. reg. 8 16 8 nws [1:0] v ref write add. decode write data reg 8 8 20 8 r/w ld r/w cq cq doff 1 m x 8 array write data reg control logic c c 8 1 m x 9 array clk a (19:0) gen. k k control logic address register d [8:0] read add. decode read data reg. ld q [8:0] reg. reg. reg. 9 18 9 bws [0] v ref write add. decode write data reg 9 9 20 9 r/w ld r/w cq cq doff 1 m x 9 array write data reg control logic c c 9 [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 3 of 31 logic block diagram (CY7C1393KV18) logic block diagram (cy7c1394kv18) 512 k x 18 array clk a (18:0) gen. k k control logic address register d [17:0] read add. decode read data reg. ld q [17:0] reg. reg. reg. 18 36 18 bws [1:0] v ref write add. decode write data reg 18 18 19 18 r/w ld r/w cq cq doff 512 k x 18 array write data reg control logic c c 18 256 k x 18 array clk a (17:0) gen. k k control logic address register d [35:0] read add. decode read data reg. ld q [35:0] reg. reg. reg. 36 72 36 bws [3:0] v ref write add. decode write data reg 36 36 18 36 r/w ld r/w cq cq doff 256 k x 18 array write data reg control logic c c 36 [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 4 of 31 contents pin configuration ............................................................. 5 pin definitions .................................................................. 7 functional overview ........................................................ 9 application example ...................................................... 10 truth table ...................................................................... 11 write cycle descriptions ............................................... 11 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 13 tap controller state diagram ....................................... 15 tap controller block diagram ...................................... 16 tap electrical characteristics ...................................... 16 tap ac switching characteristics ............................... 17 tap timing and test conditions .................................. 17 identification register definitions ................................ 18 scan register sizes ....................................................... 18 instruction codes ........................................................... 18 boundary scan order .................................................... 19 power up sequence in ddr ii s ram ............ ........... .... 20 power up sequence ................................................. 20 pll constraints ......................................................... 20 maximum ratings ........................................................... 21 operating range ............................................................. 21 neutron soft error immunity ......................................... 21 electrical characteristics ............................................... 21 dc electrical characteristics ..................................... 21 ac electrical characteristics ..................................... 23 capacitance .................................................................... 24 thermal resistance ........................................................ 24 switching characteristics .............................................. 25 switching waveforms .................................................... 27 ordering information ...................................................... 28 ordering code definitions ..... .................................... 28 package diagram ............................................................ 29 acronyms ....................................................................... 30 document conventions ................................................. 30 units of measure ....................................................... 30 document history page ................................................. 31 sales, solutions, and legal information ...................... 31 worldwide sales and design s upport ......... .............. 31 products .................................................................... 31 psoc solutions ......................................................... 31 [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 5 of 31 pin configuration the pin configurations for cy7c1392kv18, cy7c19 92kv18, CY7C1393KV18, and cy7c1394kv18 follow. [1] 165-ball fbga (13 x 15 x 1.4 mm) pinout cy7c1392kv18 (2 m x 8) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/72m a r/w nws 1 k nc/144m ld anc/36mcq b nc nc nc a nc/288m k nws 0 ancncq3 c nc nc nc v ss aaav ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v ddq v ss v ss v ss v ddq nc d2 q2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d5 q5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q1 d1 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q6 d6 v ddq v ss v ss v ss v ddq nc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss aaav ss nc nc nc p nc nc q7 a a c a a nc nc nc r tdotckaaac aaatmstdi cy7c1992kv18 (2 m x 9) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/72m a r/w nc k nc/144m ld anc/36mcq b nc nc nc a nc/288m k bws 0 ancncq4 c nc nc nc v ss aaav ss nc nc d4 d nc d5 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q5 v ddq v ss v ss v ss v ddq nc d3 q3 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d6 q6 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q2 d2 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q7 d7 v ddq v ss v ss v ss v ddq nc nc q1 m nc nc nc v ss v ss v ss v ss v ss nc nc d1 n nc d8 nc v ss aaav ss nc nc nc p nc nc q8 a a c a a nc d0 q0 r tdotckaaac aaatmstdi note 1. nc/36m, nc/72m, nc/144 m, and nc/288m are not connected to the die and can be tied to any voltage level. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 6 of 31 CY7C1393KV18 (1 m x 18) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/144m nc/36m r/w bws 1 k nc/288m ld anc/72mcq b nc q9 d9 a nc k bws 0 ancncq8 c nc nc d10 v ss aaav ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss aaav ss nc nc d1 p nc nc q17 a a c a a nc d0 q0 r tdotckaaac aaatmstdi cy7c1394kv18 (512k x 36) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/288m nc/72m r/w bws 2 k bws 1 ld nc/36m nc/144m cq b q27 q18 d18 a bws 3 kbws 0 ad17q17q8 c d27 q28 d19 v ss aaav ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss aaav ss q10 d9 d1 p q35 d35 q26 a a c a a q9 d0 q0 r tdotckaaac aaatmstdi pin configuration (continued) the pin configurations for cy7c1392kv18, cy7c19 92kv18, CY7C1393KV18, and cy7c1394kv18 follow. [1] 165-ball fbga (13 x 15 x 1.4 mm) pinout [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 7 of 31 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals. sampled on the rising edge of k and k clocks during valid write operations. cy7c1392kv18 - d [7:0] cy7c1992kv18 - d [8:0] CY7C1393KV18 - d [17:0] cy7c1394kv18 - d [35:0] ld input- synchronous synchronous load. this input is brought low wh en a bus cycle sequence is defined. this definition includes address and read/write dire ction. all transactions operate on a burst of 2 data (one clock period of bus activity). nws 0 , nws 1 nibble write select 0, 1 ? active low (cy7c1392kv18 only). sampled on the rising edge of the k and k clocks during write operations. used to select which nibble is written into the device during the current portion of the write operations.nibbles not written remain unaltered. nws 0 controls d [3:0] and nws 1 controls d [7:4] . all nibble write selects are sampled on the same edg e as the data. deselecting a nibble write select ignores the corresponding nibble of data and it is not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ? active low. sampled on the rising edge of the k and k clocks during write operations. used to select whic h byte is written into the device dur ing the current portion of the write operations. bytes not written remain unaltered. cy7c1992kv18 ?? bws 0 controls d [8:0] CY7C1393KV18 ?? bws 0 controls d [8:0] , bws 1 controls d [17:9] . cy7c1394kv18 ??? bws 0 controls d [8:0] , bws 1 controls d [17:9] ,bws 2 controls d [26:18] and bws 3 controls d [35:27]. all the byte write selects are sampled on the same edge as the data. deselecting a byte write select ignores the corresponding byte of data and it is not written into the device. a input- synchronous address inputs. sampled on the rising edge of the k clock during active read and write operations. these address inputs are multiplexed for both read and write o perations. internally, the device is organized as 2m x 8 (2 arrays each of 1m x 8) for cy7c1392kv18, 2m x 9 (2 arrays each of 1m x 9) for cy7c1992kv18, 1m x 18 (2 arrays each of 512k x 18) for CY7C1393KV18 and 512k x 36 (2 arrays each of 256k x 36) for cy7c1394kv18. therefore, only 20 address inputs are needed to access the entire memory array of cy7c1392kv18 and cy7c1992kv18, 19 address inputs for CY7C1393KV18 and 18 address inputs for cy7c1394kv18. these inputs are ignored w hen the appropriate port is deselected. q [x:0] outputs- synchronous data output signals. these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations, or k and k when in single clock mode. when the read port is deselected, q [x:0] are automatically tristated. cy7c1392kv18 ? q [7:0] cy7c1992kv18 ? q [8:0] CY7C1393KV18 ? q [17:0] cy7c1394kv18 ? q [35:0] r/w input- synchronous synchronous read/write input. when ld is low, this input designates the access type (read when r/w is high, write when r/w is low) for the loaded address. r/w must meet the setup and hold times around the edge of k. c input clock positive input clock for output data. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example on page 10 for further details. c input clock negative input clock for output data. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example on page 10 for further details. k input clock positive input clock input. the rising edge of k is used to captur e synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input clock negative input clock input. k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 8 of 31 cq echo clock cq referenced with respect to c. this is a fr ee running clock and is synchronized to the input clock for output data (c) of the ddr ii. in the single clock mo de, cq is generated with respect to k. the timings for the echo clocks is shown in the switching characteristics on page 25 . cq echo clock cq referenced with respect to c . this is a free running clock and is synchronized to the input clock for output data (c ) of the ddr ii. in the single clock mode, cq is generated with respect to k . the timings for the echo clocks is shown in the switching characteristics on page 25 . zq input output impedance matching input. this input is used to tune the device outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 x rq , where rq is a resistor connected between zq and ground. alternatively, th is pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be c onnected directly to gnd or left unconnected. doff input pll turn off ? active low. connecting this pin to ground turns off the pll inside the device. the timing in the pll turned off operation differ s from those listed in th is data sheet. for normal operation, this pin is connected to a pull up through a 10 k ohm or less pull up resistor. the device behaves in ddr i mode when the pll is turned off. in this mode, the device can be operated at a frequency of up to 167 mhz with ddr i timing. tdo output tdo for jtag. tck input tck pin for jtag. tdi input tdi pin for jtag. tms input tms pin for jtag. nc n/a not connected to the die. can be tied to any voltage level. nc/36m n/a not connected to the die. can be tied to any voltage level. nc/72m n/a not connected to the die. can be tied to any voltage level. nc/144m n/a not connected to the die. can be tied to any voltage level. nc/288m n/a not connected to the die. can be tied to any voltage level. v ref input- reference reference voltage input. static input used to set the reference level for hstl inputs, outputs, and ac measurement points. v dd power supply power supply inputs to the core of the device. v ss ground ground for the device. v ddq power supply power supply inputs for the outputs of the device. pin definitions (continued) pin name i/o pin description [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 9 of 31 functional overview the cy7c1392kv18, cy7c1992kv18, CY7C1393KV18, and cy7c1394kv18 are synchronous pipelined burst srams equipped with a ddr ii separate i/o interface, which operates with a read late ncy of one and half cycles when doff pin is tied high. when doff pin is set low or connected to v ss the device behaves in ddr i mode with a read latency of one clock cycle. accesses are initiated on the risi ng edge of the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the rising edge of the output clocks (c/c , or k/k when in single clock mode). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the rising edge of the input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising e dge of the output clocks (c/c , or k/k when in single-clock mode). all synchronous control (r/w , ld , bws [0:x] ) inputs pass through input registers controlled by the ri sing edge of the input clock (k). CY7C1393KV18 is described in the following sections. the same basic descriptions apply to cy7c1392kv18, cy7c1992kv18, and cy7c1394kv18. read operations the CY7C1393KV18 is organized internally as two arrays of 512 k x 18. accesses are completed in a burst of two sequential 18-bit data words. read operatio ns are initiated by asserting r/w high and ld low at the rising edge of the positive input clock (k). the address presented to address inputs is stored in the read address register. following the next k clock rise the corresponding lowest order 18-bit wo rd of data is driven onto the q [17:0] using c as the output timing reference. on the subsequent rising edge of c, the nex t 18-bit data word is driven onto the q [17:0] . the requested data is valid 0.45 ns from the rising edge of the output clock (c or c , or k and k when in single clock mode, for 200 mhz and 250 mhz device). read accesses can be initiated on every rising edge of the positive input clock (k). this pipelines the data flow such that data is transferred out of the device on every rising edg e of the output clocks, c/c (or k/k when in single clock mode). the CY7C1393KV18 first completes the pending read transactions, when read access is deselected. synchronous internal circuitry automatically tr istates the output following the next rising edge of the positive output clock (c). write operations write operations are initiated by asserting r/w low and ld low at the rising edge of the positive input clock (k). the address presented to address inputs is stored in the write address register. on the following k clock rise the data presented to d [17:0] is latched and stored into the 18-bit write data register, provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register, provided bws [1:0] are both asserted active. the 36 bits of data are then written into the memory array at the specified location. write accesses can be initiated on every rising edge of the positive input clock (k). this pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (k and k ). when write access is deselected, the device ignores all inputs after the pending write operations are completed. byte write operations byte write operations are supp orted by the CY7C1393KV18. a write operation is initia ted as described in the write operations section. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate byte write select input during the data portion of a write latches the data being presented and writes it into the device. deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. this feature is used to simplify read, modify, and write operations to a byte write operation. single clock mode the CY7C1393KV18 is used with a single clock that controls both the input and output registers. in this mode the device recognizes only a single pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, tie c and c high at power on. this function is a strap optio n and not alterable during device operation. ddr operation the CY7C1393KV18 enables high performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. if a read occurs after a write cycle, address and data for the write are stored in registers. the write information must be stored because the sram cannot perform the last word write to the array without conflicting with the read. the data stays in this register until the next write cycle o ccurs. on the first write cycle after the read(s), the stored data fr om the earlier write is written into the sram array. this is called a posted write. depth expansion depth expansion requir es replicating the ld control signal for each bank. all other control signals can be common between banks as appropriate. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedanc e matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq = 1.5 v. the output impedance is adjusted ever y 1024 cycles at power up to account for drifts in supply voltage and temperature. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 10 of 31 echo clocks echo clocks are provided on the ddr ii to simplify data capture on high speed systems. two echo clocks are generated by the ddr ii. cq is referenced with respect to c and cq is referenced with respect to c . these are free running clocks and are synchronized to the output clock of the ddr ii. in the single clock mode, cq is generated with respect to k and cq is generated with respect to k . the timing for the echo clocks is shown in switching characteristics on page 25 . pll these chips use a phase locked loop (pll) that is designed to function between 120 mhz and the specified maximum clock frequency. during power up, when the doff is tied high, the pll is locked after 20 ? s of stable clock. the pll can also be reset by slowing or stoppi ng the input clocks k and k for a minimum of 30 ns. however, it is not necessary to reset the pll to lock it to the desired fre quency. the pll automatically locks 20 ? s after a stable clock is presented. the pll may be disabled by applying ground to the doff pin. when the pll is turned off, the device behaves in ddr i mo de (with one cycle latency and a longer access time). application example figure 1 shows four ddr ii sio used in an application. figure 1. application example ld # r/w # b w # vt = v ref cc# cq cq# k# zq q d k cc# k bus master (cpu or asic) sram 1 sram 4 data in data out address ld# r/w# bws# sram 1 input cq sram 1 input cq# sram 4 input cq sram 4 input cq# source k source k# delayed k delayed k# r=50 ohms r = 250 ohms cq cq# k# zq q ld # r/w # b w s # ld # r/w # vt vt vt r r r a a d r = 250 ohms b w s # [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 11 of 31 truth table the truth table for cy7c1392kv18, cy7c1992kv18, CY7C1393KV18, and cy7c1394kv18 follows. [2, 3, 4, 5, 6, 7] operation k ld r/w dq dq write cycle: load address; wait one cycle; input write data on consecutive k and k rising edges. l-h l l d(a + 0) at k(t + 1) ? d(a + 1) at k (t + 1) ? read cycle: load address; wait one and a half cycle; read data on consecutive c and c rising edges. l-h l h q(a + 0) at c (t + 1) ? q(a + 1) at c(t + 2) ? nop: no operation l-h h x high-z high-z standby: clock stopped stopped x x previous state previous state write cycle descriptions the write cycle description table for cy 7c1392kv18 and CY7C1393KV18 follows. [2, 8] bws 0 / nws 0 bws 1 / nws 1 k k comments l l l?h ? during the data portion of a write sequence ? cy7c1392kv18 ?? both nibbles (d [7:0] ) are written into the device. CY7C1393KV18 ?? both bytes (d [17:0] ) are written into the device. l l ? l-h during the data portion of a write sequence ? cy7c1392kv18 ?? both nibbles (d [7:0] ) are written into the device. CY7C1393KV18 ?? both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence ? cy7c1392kv18 ?? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. CY7C1393KV18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence ? cy7c1392kv18 ?? only the lower nibble (d [3:0] ) is written into the device, d [7:4] remains unaltered. CY7C1393KV18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l?h ? during the data portion of a write sequence ? cy7c1392kv18 ?? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. CY7C1393KV18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l?h during the data portion of a write sequence ? cy7c1392kv18 ?? only the upper nibble (d [7:4] ) is written into the device, d [3:0] remains unaltered. CY7C1393KV18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l?h ? no data is written into the devices during this portion of a write operation. h h ? l?h no data is written into the devices during this portion of a write operation. notes 2. x = ?don't care?, h = logic high, l = logic low, ? represents rising edge. 3. device powers up deselected with the outputs in a tristate condition. 4. ?a? represents address location latched by the devices when transaction was initiated. a + 0, a + 1 represents the internal a ddress sequence in the burst. 5. ?t? represents the cycle at which a read/write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. ensure that when the clock is stopped k = k and c = c = high. th is is not essential, but permits most rapid restart by overco ming transmission line charging symmetrically. 8. is based on a write cycle that was initiated in accordance with the write cycle descriptions table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 ,and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 12 of 31 write cycle descriptions the write cycle description ta ble for cy7c1992kv18 follows. [9, 10] bws 0 k k comments l l?h ? during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. l ? l?h during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. h l?h ? no data is written into the device during this portion of a write operation. h ? l?h no data is written into the device during this portion of a write operation. write cycle descriptions the write cycle description ta ble for cy7c1394kv18 follows. [9, 10] bws 0 bws 1 bws 2 bws 3 k k comments lllll?h?during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. llll?l?hduring the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l?h ? during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. hhhhl?h?no data is written into the device during this portion of a write operation. hhhh?l?hno data is written into the device during this portion of a write operation. notes 9. x = ?don't care?, h = logic high, l = logic low, ? represents rising edge. 10. is based on a write cycle that was initiated in accordance with the write cycle descriptions table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 ,and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 13 of 31 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-2001. the tap operates using jedec standard 1.8 v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. up on power up, the device comes up in a reset state, which does not in terfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction register, see the tap controller state diagram on page 15. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active, depending upon the current state of the tap state machine (see instruction codes on page 18). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and is performed when the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions are serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 16. upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board level serial test path. bypass register to save time when serially shifti ng data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this enables shifting of data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions are used to capture the contents of the input and output ring. the boundary scan order on page 19 shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and is shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in identification register definitions on page 18. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in instruction codes on page 18. three of these instructions are listed as reserved and must not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instru ctions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction after it is shif ted in, the tap controller must be moved into the update-ir state. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 14 of 31 idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power up or whenever the tap controller is supplied a test-logic-reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the nex t command is supplied during the update ir state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instruct ions are loaded into the instruction register and the tap c ontroller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is l oaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction drives the preloaded data out through the system output pins. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tristate ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tristate mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the ?extest output bus tristate,? is latched into the preload register during the update-dr state in the tap controller, it directly controls the stat e of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high-z condition. this bit is set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is pre-set low to enable the output when the device is powered up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not implemented but are reserved for future use. do not use these instructions. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 15 of 31 tap controller state diagram the state diagram for the tap controller follows. [11] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 11. the 0/1 next to each state represents the value at tms at the rising edge of tck. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 16 of 31 tap controller block diagram tap electrical ch aracteristics over the operating range [12, 13, 14] parameter description test conditions min max unit v oh1 output high voltage i oh = ?? 2.0 ma 1.4 ? v v oh2 output high voltage i oh = ?? 100 ? a1.6?v v ol1 output low voltage i ol = 2.0 ma ? 0.4 v v ol2 output low voltage i ol = 100 ? a?0.2v v ih input high voltage ? 0.65 v dd v dd + 0.3 v v il input low voltage ? ?0.3 0.35 v dd v i x input and output load current gnd ? v i ? v dd ?5 5 ? a 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms notes 12. these characteristics pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics table. 13. overshoot: v ih (ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 1.5 v (pulse width less than t cyc /2). 14. all voltage referenced to ground. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 17 of 31 tap ac switchi ng characteristics over the operating range [15, 16] parameter description min max unit t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high 20 ? ns t tl tck clock low 20 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns tap timing and test conditions figure 2 shows the tap timing and test conditions. [16] figure 2. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9 v 50 ? 1.8 v 0 v all input pulses 0.9 v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo notes 15. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 16. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 18 of 31 identification regi ster definitions instruction field value description cy7c1392kv18 cy7c1992kv18 CY7C1393KV18 cy7c1394kv18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010100010000101 11010100010001101 11010100010010101 11010100010100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output contents. places the bou ndary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input and output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 19 of 31 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 28 10g 56 6a 84 2j 16p299g575b853k 2 6n 30 11f 58 5a 86 3j 3 7p 31 11g 59 4a 87 2k 47n 329f 605c 881k 5 7r 33 10f 61 4b 89 2l 6 8r 34 11e 62 3a 90 3l 7 8p 35 10e 63 1h 91 1m 8 9r 36 10d 64 1a 92 1l 9 11p 37 9e 65 2b 93 3n 10 10p 38 10c 66 3b 94 3m 11 10n 39 11d 67 1c 95 1n 12 9p 40 9c 68 1b 96 2m 13 10m 41 9d 69 3d 97 3p 14 11n 42 11b 70 3c 98 2n 15 9m 43 11c 71 1d 99 2p 16 9n 44 9b 72 2c 100 1p 17 11l 45 10b 73 3e 101 3r 18 11m 46 11a 74 2d 102 4r 19 9l 47 internal 75 2e 103 4p 20 10l 48 9a 76 1e 104 5p 21 11k 49 8b 77 2f 105 5n 22 10k 50 7c 78 3f 106 5r 23 9j 51 6c 79 1g 24 9k 52 8a 80 1f 25 10j 53 7a 81 3g 26 11j 54 7b 82 2g 27 11h 55 6b 83 1j [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 20 of 31 power up sequence in ddr ii sram ddr ii srams must be powered up and initialized in a predefined manner to prevent undefined operations. power up sequence apply power and drive doff either high or low (all other inputs can be high or low). ? apply v dd before v ddq . ? apply v ddq before v ref or at the same time as v ref . ? drive doff high. provide stable doff (high), power and clock (k, k ) for 20 ? s to lock the pll. pll constraints pll uses k clock as its synchronizing input. the input must have low phase jitter, which is specified as t kc var . the pll functions at frequencies down to 120 mhz. if the input clock is unstable and the pll is enabled, then the pll may lock onto an incorrect frequency, causing unstable sram behavior. to avoid this, provide 20 ? s of stable clock to relock to the desired clock frequency. figure 3. power up waveforms > 20 p s stable clock start normal operation doff stabl e (< +/- 0.1v dc per 50ns ) fix high (or tie to v ddq ) k k ddq dd v v / ddq dd v v / clock start ( clock starts after stable ) ddq dd v v / ~ ~ ~ ~ unstable clock [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 21 of 31 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied . ?55 c to +125 c supply voltage on v dd relative to gnd ........?0.5 v to +2.9 v supply voltage on v ddq relative to gnd....... ?0.5 v to +v dd dc applied to outputs in high-z ....... ?0.5 v to v ddq + 0.3 v dc input voltage [17] ............................ ?0.5 v to v dd + 0.3 v current into outputs (low) ......................................... 20 ma static discharge voltage (mil-std-883, m. 3015).. > 2001 v latch up current..................................................... > 200 ma operating range range ambient temperature (t a ) v dd [19] v ddq [19] commercial 0 c to +70 c 1.8 0.1 v 1.4 v to v dd industrial ?40 c to +85 c neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 197 216 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculation. for more details refer to appli- cation note, accelerated neutron ser testing and calculation of terrestrial failure rates - an54908. electrical characteristics dc electrical characteristics over the operating range [18] parameter description test conditions min typ max unit v dd power supply voltage ? 1.7 1.8 1.9 v v ddq i/o supply voltage ? 1.4 1.5 v dd v v oh output high voltage note 20 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v ol output low voltage note 21 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?? 0.1 ma, nominal impedance v ddq ? 0.2 ? v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss ? 0.2 v v ih input high voltage ? v ref + 0.1 ? v ddq + 0.3 v v il input low voltage ? ?0.3 ? v ref ? 0.1 v i x input leakage current gnd ? v i ? v ddq ? 5 ? 5 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ? 5 ? 5 ? a v ref input reference voltage [22] typical value = 0.75 v 0.68 0.75 0.95 v notes 17. overshoot: v ih (ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il (ac) > ? 1.5 v (pulse width less than t cyc /2). 18. all voltage referenced to ground. 19. power up: assumes a linear ramp from 0 v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 20. outputs are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 21. outputs are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 22. v ref (min) = 0.68 v or 0.46 v ddq , whichever is larger, v ref (max) = 0.95 v or 0.54 v ddq , whichever is smaller. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 22 of 31 i dd [23] v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 333 mhz (x8) ? ? 440 ma (x9) ? ? 440 (x18) ? ? 450 (x36) ? ? 560 300 mhz (x8) ? ? 420 ma (x9) ? ? 420 (x18) ? ? 430 (x36) ? ? 520 250 mhz (x8) ? ? 370 ma (x9) ? ? 370 (x18) ? ? 380 (x36) ? ? 460 200 mhz (x8) ? ? 330 ma (x9) ? ? 330 (x18) ? ? 340 (x36) ? ? 400 167 mhz (x8) ? ? 300 ma (x9) ? ? 300 (x18) ? ? 310 (x36) ? ? 360 electrical characteristics (continued) dc electrical characteristics over the operating range [18] parameter description test conditions min typ max unit note 23. the operation current is calculated with 50% read cycle and 50% write cycle. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 23 of 31 i sb1 automatic power down current max v dd , both ports deselected, v in ? v ih or v in ? v il f = f max = 1/t cyc , inputs static 333 mhz (x8) ? ? 270 ma (x9) ? ? 270 (x18) ? ? 270 (x36) ? ? 270 300 mhz (x8) ? ? 260 ma (x9) ? ? 260 (x18) ? ? 260 (x36) ? ? 260 250 mhz (x8) ? ? 250 ma (x9) ? ? 250 (x18) ? ? 250 (x36) ? ? 250 200 mhz (x8) ? ? 250 ma (x9) ? ? 250 (x18) ? ? 250 (x36) ? ? 250 167 mhz (x8) ? ? 250 ma (x9) ? ? 250 (x18) ? ? 250 (x36) ? ? 250 ac electrical characteristics over the operating range [13] parameter description test conditions min typ max unit v ih input high voltage ? v ref + 0.2 ? ? v v il input low voltage ? ? ? v ref ? 0.2 v electrical characteristics (continued) dc electrical characteristics over the operating range [18] parameter description test conditions min typ max unit [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 24 of 31 capacitance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 1.8 v, v ddq = 1.5 v 4 pf c o output capacitance 4pf thermal resistance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 165 fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuri ng thermal impedance, in accordance with eia/jesd51. 13.7 c/w ? jc thermal resistance (junction to case) 3.73 c/w figure 4. ac test loads and waveforms 1.25 v 0.25 v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75 v v ref = 0.75 v [24] 0.75 v under te s t 0.75 v device under te s t output 0.75 v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ? 24. unless otherwise noted, test conditions are based on signal trans ition time of 2 v/ns, timing reference levels of 0.75 v, vr ef = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads and waveforms . [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 25 of 31 switching characteristics over the operating range [25, 26] cypress parameter consortium parameter description 333 mhz 300 mhz 250 mhz 200 mhz 167 mhz unit min max min max min max min max min max t power v dd (typical) to the first access [27] 1?1?1?1?1?ms t cyc t khkh k clock and c clock cycle time 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns t kh t khkl input clock (k/k ; c/c ) high 1.20 ? 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns t kl t klkh input clock (k/k ; c/c ) low 1.20 ? 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns t khk h t khk h k clock rise to k clock rise and c to c rise (rising edge to rising edge) 1.35 ? 1.49 ? 1.8 ? 2.2 ? 2.7 ? ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0 1.30 0 1.45 0 1.8 0 2.2 0 2.7 ns setup times t sa t avkh address setup to k clock rise 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns t sc t ivkh control setup to k clock rise (ld , r/w ) 0.4?0.4?0.5?0.6?0.7? ns t scddr t ivkh double data rate control setup to clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.3?0.3?0.35?0.4?0.5? ns t sd t dvkh d [x:0] setup to clock (k/k ) rise 0.3?0.3?0.35?0.4?0.5? ns hold times t ha t khax address hold after k clock rise 0.4?0.4?0.5?0.6?0.7? ns t hc t khix control hold after k clock rise (ld , r/w ) 0.4?0.4?0.5?0.6?0.7? ns t hcddr t khix double data rate control hold after clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.3?0.3?0.35?0.4?0.5? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.3?0.3?0.35?0.4?0.5? ns notes 25. unless otherwise noted, test conditions are based on signal trans ition time of 2 v/ns, timing reference levels of 0.75 v, vr ef = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads and waveforms . 26. when a part with a maximum frequency above 167 mhz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range. 27. this part has a voltage regulator internally; t power is the time that the power must be supplied above v dd minimum initially before a read or write operation can be initiated. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 26 of 31 output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.50 ns t doh t chqx data output hold after output c/c clock rise (active to active) ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.50 ? ns t ccqo t chcqv c/c clock rise to echo clock valid ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.50 ns t cqoh t chcqx echo clock hold after c/c clock rise ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.50 ? ns t cqd t cqhqv echo clock high to data valid 0.25 0.27 0.30 0.35 0.40 ns t cqdoh t cqhqx echo clock high to data invalid ?0.25 ? ?0.27 ? ?0.30 ? ?0.35 ? ?0.40 ? ns t cqh t cqhcql output clock (cq/cq ) high [28] 1.25 ? 1.40 ? 1.75 ? 2.25 ? 2.75 ? ns t cqhcq h t cqhcq h cq clock rise to cq clock rise (rising edge to rising edge) [28] 1.25 ? 1.40 ? 1.75 ? 2.25 ? 2.75 ? ns t chz t chqz clock (c/c ) rise to high-z (active to high-z) [29, 30] ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.50 ns t clz t chqx1 clock (c/c ) rise to low-z [29, 30] ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.50 ? ns pll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ? 0.20 ? 0.20 ? 0.20 ns t kc lock t kc lock pll lock time (k, c) 20?20?20?20?20? ? s t kc reset t kc reset k static to pll reset 3030303030 ns switching characteristics (continued) over the operating range [25, 26] cypress parameter consortium parameter description 333 mhz 300 mhz 250 mhz 200 mhz 167 mhz unit min max min max min max min max min max notes 28. these parameters are extrapolated from the input timing parameters (t cyc /2 - 250 ps, where 250 ps is the internal jitter). these parameters are only guaranteed by design and are not tested in production 29. t chz , t clz , are specified with a load capacitance of 5 pf as in (b) of ac test loads and waveforms . transition is measured 100 mv from steady-state voltage. 30. at any voltage and temperature t chz is less than t clz and t chz less than t co . [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 27 of 31 switching waveforms figure 5. read/write/deselect sequence [31, 32, 33] k 1234567 8 k ld r/w a q d c c# read (burst of 2) read (burst of 2) read (burst of 2) write (burst of 2) write (burst of 2) t khch t khch nop nop cq cq# t kh t khkh t co t kl t cyc t t hc t sa t ha t sd t hd t sd t hd t clz t doh sc t kh t khkh t kl t cyc t cqd t ccqo t cqoh t ccqo t cqoh dont care undefined a0 a1 a2 a3 a4 d20 d21 d30 d31 q40 q11 q10 q41 q00 q01 t cqdoh t cqh t cqhcqh t chz notes 31. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, that is, a0+1. 32. outputs are disabled (high-z) one clock cycle after a nop. 33. in this example, if address a4 = a3, then data q40 = d30 and q41 = d31. write data is forwarded immediately as read results. this note applies to the whole diagram. [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 28 of 31 ordering information the following table contains only the parts that are currently av ailable. if you do not see what you are looking for, contact y our local sales representative. for more informa tion, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices. table 2. ordering information speed (mhz) ordering code package diagram package type operating range 250 CY7C1393KV18-250bzi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial 300 CY7C1393KV18-300bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) pb-free commercial 333 CY7C1393KV18-333bzi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial ordering code definitions temperature range: i = industrial = ?40 ? c to +85 ? c; c = commercial = 0 ? c to +70 ? c x = pb-free; x absent = leaded package type: bz = 165-ball fpbga speed grade: xxx = 333 mhz / 250 mhz v18 = 1.8 v v dd process technology ? 65 nm 1393 = part identifier marketing code: 7c = srams company id: cy = cypress cy 13xx k - xxx bz x v18 i 7c [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 29 of 31 package diagram figure 6. 165-ball fbga (13 x 15 x 1.4 mm), 51-85180 a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.08 m c b a 0.15(4x) seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 -0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / issue e package code : bb0ac 51-85180-*c [+] feedback
cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 document number: 001-58907 rev. *b page 30 of 31 acronyms document conventions units of measure acronym description ce chip enable cen clock enable ddr double data rate fpbga fine-pitch ball grid array hstl high-speed transceiver logic i/o input/output jtag joint test action group lmbu logical multiple bit upset lsbu logical single bit upset oe output enable pll phase locked loop sel single event latch up tck test clock tms test mode select tdi test data-in tdo test data-out tqfp thin quad flat pack we write enable symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes ms milli seconds mhz mega hertz pf pico farad wwatts c degree celcius [+] feedback
document number: 001-58907 rev. *b revised february 25, 2011 page 31 of 31 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oduct and company names mentioned in this document are the trademarks of their respective holders. cy7c1392kv18, cy7c1992kv18 CY7C1393KV18, cy7c1394kv18 ? cypress semiconductor corporation, 2010-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document history page document title: cy7c1392kv18/cy7c1992kv18/cy7c 1393kv18/cy7c1394kv18, 18-mbit ddr ii sio sram two-word burst architecture document number: 001-58907 rev. ecn no. orig. of change submission date description of change ** 2860800 vkn 01/20/2010 new datasheet *a 3081152 njy 11/09/2010 changed status from preliminary to final. updated ordering information. added ordering code definitions. added acronyms and document conventions. *b 3181564 shtc 02/25/2011 added part CY7C1393KV18-300bzxc in ordering information [+] feedback

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